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[VHDL-FPGA-Verilog] 8051IPcore，verilogHDL实现

Description: 用verilog写的很好的cpu core-using Verilog write a good cpu core
Platform: | Size: 52224 | Author: 刘烨波 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio/video codec
Platform: | Size: 222208 | Author: | Hits:

[Crack Hack] aes_core

Description: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Platform: | Size: 79872 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] AUDIO_DAC

Description: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Platform: | Size: 2048 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] S2P_xapp194

Description: VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
Platform: | Size: 26624 | Author: 苏翔 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[Embeded-SCM Develop] NIOS_II_IP

Description: 基于双NIOS II 的IP无线收发机 2006年嵌入式电子大赛获奖作品-NIOS II-based IP wireless transceiver embedded electronic 2006 Championship winning entries
Platform: | Size: 381952 | Author: 刘斐 | Hits:

[VHDL-FPGA-Verilog] my_ip_core

Description: 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
Platform: | Size: 51200 | Author: 刘海 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: crc校验，非常好用，是从Xilinx的IP演化来的-crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟
Platform: | Size: 10240 | Author: zl | Hits:

[VHDL-FPGA-Verilog] fft_IPcore

Description: 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
Platform: | Size: 8719360 | Author: 李杰 | Hits:

[VHDL-FPGA-Verilog] NCO_ip

Description: NCO的VHDL程序，是利用IP核生成的，超好的，快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
Platform: | Size: 128000 | Author: 张俊 | Hits:

[Software Engineering] Wishbone_from_opencores

Description: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applications, wishbone bus is also becoming increasingly popular.
Platform: | Size: 836608 | Author: 刘庆强 | Hits:

[VHDL-FPGA-Verilog] VGA_LCD_IP

Description: vga ipcore的verilog代码
Platform: | Size: 495616 | Author: | Hits:

[VHDL-FPGA-Verilog] CAN_IPCore

Description: CAN_IPCore CAN协议的IP核源代码 verilog 语言
Platform: | Size: 61440 | Author: maliang | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:
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